EML-MPC1

March 8, 2026

The MPC 1 or is it 0? Features a AM9511DC-1DC FPU from AMD. The curious thing is that the box says MPC 1 with a 0 written over the 1^[1], I'd love to know why. I've been faffing about with it for a couple of weeks now, without documentation it's slow progress and I think I've almost reached my limit.

I've not finished reverse engineering the board yet, there's still a bit to do. I have copied the firmware and I've done a decompile of it, binary [here] and decompile [here].

A quick run down of the hardware on the board^[2]. I'll do another post with findings and operation.

MPC1 Hardware Summary

THe MPC1 has its own CPU, I/O controller, and arithmetic processor - completely independent from the host CPC-8.

Core Processors

• Z80A (Z8400A) - Main CPU, possibly running at 2Mhz
• AM9511-10C - Arithmetic Processing Unit (APU), handles integer, float, and transcendental math; 3 MHz capable, clocked at 2 MHz
• Z80A PIO - Parallel I/O controller; manages FIFO status flags, AM9511 completion signals, and Z80 reset control

Memory

• D2716-1 - 2KB UV-EPROM, firmware source, mapped to $0000
• L2114-2CE ×2 - 1K×4 SRAM (making 1K×8 total working RAM)
• M3-7621-5 - 512×4 bipolar PROM (address decoder)
• HM3-7611-5 - 256×4 bipolar PROM (backplane decode, controls data bus transceiver and PIO /CE)

Bus Interface

• SN74LS245N - Bidirectional octal transceiver (data bus, tri-stated during normal operation)
• DM74LS244N - Octal buffer (address/data bus buffering from system bus)
• 74LS85N - 4-bit comparator (DIP switch I/O page decode, base address $2x)

Communication (Host ↔ MPC1)

• W21510F-01 ×2 (WD1510-equivalent async FIFOs) - one output, one input

Glue Logic & Clocking

• DM74LS161N - 4-bit counter, divides 8 MHz crystal down to 2 MHz for the Z80 and APU
• DH74LS00N ×2 - Quad NAND gates; generate FIFO chip-select strobes and AM9511 /CS
• SN74LS08N - Quad AND gate; FIFO enable logic, Z80 /RESET, and PIO /M1 decode

Power

• OL-13 / 6410-150 - DC-DC converter providing +12V (VBB) required by the AM9511 APU

Notable Design Points

• The Z80 /RESET is jointly controlled by the backplane /PWRRCLP signal AND PIO Port B bit 0 - software can hold or release the Z80
• Clock selection is via a jumper block (currently QB ÷4 = 2 MHz, synchronous with the Z80)

There's a nummber of jumper blocks on the board to control

Jumper Blocks

Jumper Block 1 — Memory Map

• 5–6 — Powers the M3-7621-5 address decoder PROM
• 8–9 — Grounds the PROM
• 10–11 — Alternate memory map (forces A8 LOW on the PROM)

Jumper Block 2 — Clock Divider

Selects the clock fed to the AM9511 APU from the 74LS161 counter (driven by the 8 MHz crystal):

• 14–15 (current setting) — Selects QB output (÷4) = 2 MHz, synchronous with the Z80

Jumper Block 3 — Interrupt Daisy Chain ("4312")

Connects the MPC1 into the Z80 interrupt daisy chain on the backplane:

• 1–2 — Connects backplane IEI to MPC1 IEI
• 4–3 — Connects MPC1 IEO to backplane IEO