February 15, 2026

Overview

The EML/CPC-8 is a Eurolog ECB designed by FURRERGLOOR, it's main features are:

• A Z80A
• Two serial channels (V.24/RS-232) with a dual baud-rate generator (50 to 19,200 baud).
• A Z80A-PIO providing 16 bits of programmable parallel I/O.
• A Z80A-CTC (Counter/Timer Circuit) with four channels for timing and event counting.
• A real-time pulse generator (20 or 200 msec).

Since my Z80 homebrew works and can load things like CP/M^[1] and fuzix^[2], it's a known good place to start in getting the CPC8 working. I can configure the CPC8 into 'mode 8' so it ignores it's on board memory sockets and therefore use the RAM/ROM card I've been using with the homebrew Z80^[3].

Port conflicts and mapping

One Problem, though, is that my RAM/ROM card uses port 0x02 for its RAM banking and that is already in use on the CPC8.

Here is a list of ports in use, I can't change the port on my RAM banking to anything too high without redesigning it since I don't decode address A7 or above.

I can reporgram the GAL on my RAM/ROM board to slide itself into that gap at 0x08 (and techincally 0x88) and I should be able to use my existing serial port boards to comminicate with it.

Clock speed and baud rate

While my homebrew runs at 8Mhz, the CPC8 only runs at 4.9152Mhz^[4]. This means I have to lower my buad rate from 115200 to 38400. This could be somewhat promlematic in the future, on my homebrew system it takes ~3 minutes to load Fuzix at 115200 so at 38400 thats going to be around 9 minutes and if I were to use 19200 thats ~18 minutes!^[5] A problem for future me, I will probably have to use the hard drive card or the floppy controller in the future to load data

The serial port

The CPC8 has space for a DC/DC converter for generating +/-12V for use with the two serial ports, notice I said space, because mine isn't populated. It relies on the backplane to provide the +12V. I don't particually want to start messing around supplying 12V onto my backplane... So I will continue to use my homebrew serial board for now.

RAM banking test

So with the modifications to my RAM/ROM board I wrote a quick test for the RAM banking^[6]:

RAM Bank Independence Test v1.6
===============================
Tests if 16 banks are truly separate RAM

Phase 1: Writing unique value to each bank
  (Writing bank# to $0000, $2000, $4000)
  Bank $00 <- $00
  Bank $01 <- $01
  Bank $02 <- $02
  Bank $03 <- $03
  Bank $04 <- $04
  Bank $05 <- $05
  Bank $06 <- $06
  Bank $07 <- $07
  Bank $08 <- $08
  Bank $09 <- $09
  Bank $0A <- $0A
  Bank $0B <- $0B
  Bank $0C <- $0C
  Bank $0D <- $0D
  Bank $0E <- $0E
  Bank $0F <- $0F

Phase 2: Verifying each bank retained its value
  (If banks are independent, each has unique value)
  Bank $00 expect $00 got 00 00 00  [PASS]
  Bank $01 expect $01 got 01 01 01  [PASS]
  Bank $02 expect $02 got 02 02 02  [PASS]
  Bank $03 expect $03 got 03 03 03  [PASS]
  Bank $04 expect $04 got 04 04 04  [PASS]
  Bank $05 expect $05 got 05 05 05  [PASS]
  Bank $06 expect $06 got 06 06 06  [PASS]
  Bank $07 expect $07 got 07 07 07  [PASS]
  Bank $08 expect $08 got 08 08 08  [PASS]
  Bank $09 expect $09 got 09 09 09  [PASS]
  Bank $0A expect $0A got 0A 0A 0A  [PASS]
  Bank $0B expect $0B got 0B 0B 0B  [PASS]
  Bank $0C expect $0C got 0C 0C 0C  [PASS]
  Bank $0D expect $0D got 0D 0D 0D  [PASS]
  Bank $0E expect $0E got 0E 0E 0E  [PASS]
  Bank $0F expect $0F got 0F 0F 0F  [PASS]

Phase 3: Boundary Detection
  (Finding where banked RAM ends)
  $6000: AA BANKED
  $7F00: AA BANKED
  $8000: 55 FIXED
  $A000: 55 FIXED
  $B000: 55 FIXED

========== SUMMARY ==========
Passed: 16
Failed: 0

*** ALL BANKS INDEPENDENT ***

Excellent! Not only are we executing code on the CPC8 CPU but RAM banking and the homebrew serial port are working as expected.

CTC timer

Let's try the CTC next and see if we can get that working.

========================================
  CPC8 CTC Diagnostic v1.0
========================================

--- TEST 1: Raw CTC Register Read ---
  Ch0 ($0C): $FF
  Ch1 ($0D): $FF
  Ch2 ($0E): $FF
  Ch3 ($0F): $FF

--- TEST 2: Polled Timer (no IRQ) ---
  Counter reads: D6 CF C7 C0 B8 B1 A9 A2
  After 100ms:   DA D6 CF C7 C0 B8 B1 A9

--- TEST 3: IM2 Timer Interrupt ---
  Vector table at $BE00...
  ISR copied to $BF00 (17 bytes)
  Verify @$BF00: F5 E5 21
  IM2 set, I=$BE
  CTC Ch0: Timer /256, TC=96 (10ms)
  EI - dots=IRQs, #=100 IRQs (~1s)
....................................................................................................#
....................................................................................................#

Working, excellent! Oh, but wait a minute, those # should be every ~1 second but they're more like ~2.5 seconds. A scope on the CLK shows it's running at ~2.4576Mhz and the crystal on the board is 4.9152Mhz. Ah the documentation and the circuit diagram show it should be an 8Mhz crystal! Looking at the board it looks like it's been replaced at some point [picture].

More investigation needed!